[GSoC] Better RISC-V support, week #2
Last week, I updated my copy of spike (to commit 2fe8a17a), and familiarized myself with the differences between the old and the new version: The Host-Target Interface (HTIF) isn’t accessed through the...
View Article[GSoC] Multiple status registers, block protection and OTP support, week #1...
Hi, I am Hatim Kanchwala (hatim on IRC) from India. I am the GSoC student working with flashrom this year. Stefan Tauner (stefanct) and David Hendricks (dhendrix) will be mentoring me (thanks a lot for...
View Article[GSOC] Panic Room, week #2
How was your last week? Let’s say that it was a bit unexpected. I spent the majority of it trying to wrap my head around the ELF (Executable Linkable Format) specification. I used this new acquired...
View Article[GSoC] Better RISC-V support, week #3
Last week, after updating GCC (by applying Iru Cai’s patch) and commenting out uses of outdated instructions and CSRs (most notably eret and the HTIF CSRs), I noticed that coreboot crashed when it...
View Article[GSoC] Better RISC-V support, week #4/5
Week 4 In week 4, I tracked down why coreboot halted after about one line of output. It turned out to be a spike bug, that I wrote up in this bug report, and affect any program that doesn’t have a...
View Article[GSoC] Better RISC-V support, week #6/7/8/9
Since I haven’t posted an update of my coreboot-on-RISC-V work in a while, this will be a slightly longer post. Week 6 In week 6, I started documenting how to build and boot coreboot on RISC-V, in the...
View Article[GSoC] Multiple status registers, block protection and OTP support, week #6,...
Hello! I have been away for some time now, so this is going to be a longer post. I hope you have missed hearing from me 😛 In this post I will talk about my work in the weeks post-midterm evaluations....
View Article[GSoC] Better RISC-V Support, week #10
This past week, I worked on the virtual memory initialization code of coreboot on RISC-V. The first part of this was to update encoding.h a file that defines constants such as bit masks which are...
View Article[GSoC] Better RISC-V support, wrap-up
In less than an hour, Google Summer of Code 2016 will be over (at least for us students). In this blog post, I will describe how you can use coreboot on RISC-V. You can find the complete list of...
View Article[GSoC] Multiple status registers, block protection and OTP support, wrap-up...
Hello! 🙂 GSoC 2016 coding period has come to an end and mentor’s evaluating students this week. It has been an enriching 13 weeks of reading datasheets, designing structures, coding, learning and...
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